Tuesday, January 18

Doubling performance and reducing consumption by 85%: this is how vertical VTFET transistors seek to rewrite the rules of semiconductors


The semiconductor technology that aspires to succeed the FinFET transistors that we can find in most of today’s high integration chips is already looming on the horizon. In recent months, Intel has gradually unveiled the innovations it is working on to develop its integration technology with an ambitious purpose: to make Moore’s law remain in effect beyond 2025.

However, this is not the only high integration semiconductor manufacturer pursuing this goal. As we briefly anticipated two days ago, IBM and Samsung have revealed that they are working together to develop a new type of transistors designed to tear down the limitations imposed by current FinFET technology.

Your first prototypes are ready, and they promise. They promise a lot. Nothing less than doubling the performance and reduce consumption by up to 85% of the most advanced technology available today. Curiously, to make these improvements possible, the engineers of these companies have reimagined the structure of the transistors incorporated in integrated circuits. And they have done it in a very ingenious way.

The search for more space in the chips is tied to the vertical transistors

The effort in the field of innovation that companies such as ASML, TSMC, Intel, Samsung or GlobalFoundries, among other semiconductor producers, have made in recent years, has been aimed at refine your photolithographic processes to fit more transistors in the same space. Said like that it may not seem like a big deal, but in reality, the challenges that need to be overcome in packing more and more transistors inside a chip are very numerous.

The challenges that must be overcome in order to pack more and more transistors inside a chip are very numerous

The more complex details aside, the strategy that semiconductor research people have used in recent years to develop integration technology seeks to act, among other parameters, on the minimum distance between the gates of two adjacent transistors (this factor is known in English as contacted gate pitch), and also on the minimum distance that exists between two horizontal interconnections (known as metal pitch).

The problem is that the FinFET technology in use today can not do much more of itself. Of course, we have to thank him for bringing us here and for making possible the development of chips that agglutinate tens of billions of transistorsBut if we want to sustain the pace of development of recent years, it is necessary to develop a different strategy. And what IBM and Samsung are proposing sounds good.

Fet

In this scheme we can clearly see that the layers that make up the FET transistors are arranged horizontally on the wafer, so that the electric current flows in the horizontal dimension.

Current transistors with FET configuration are made up of several layers arranged horizontally on the wafer, so that the electric current flows in the horizontal dimension, circulating from one layer to another. This distribution of the transistors makes it necessary to isolate each other to prevent them from interfering, and, of course, these insulating elements take up space.

Vertical VTFET transistors take up less space than conventional transistors, so it is possible to incorporate many more in an integrated circuit

The solution that IBM and Samsung engineers have come up with to solve the limitations imposed by this topology is ingenious, but also absolutely reasonable: stacking the layers that make up the transistors. in the vertical dimension on the wafer, and not horizontally.

In this way the electric current flows vertically from one layer to another. However, the most important thing is that vertical VTFET transistors (Vertical-Transport Nanosheet Field Effect Transistor) take up less space than conventional transistors, so it is possible to incorporate many more into an integrated circuit.

Vtfet

In VTFET transistors, the layers are arranged vertically on the wafer surface, so electrical current also flows vertically from one layer to another. This configuration is intended to replace the FinFET technology currently used in the manufacture of highly integrated chips.

By directing the flow of electrical current vertically it is possible further reduce the minimum distance between the gates of two adjacent transistors (the contacted gate pitch of which we have spoken a few lines above).

And, in addition, the elements that in the FET configuration are responsible for isolating some transistors from others are no longer necessary. This is what, according to IBM, allows VTFET technology to dramatically increase integration density versus FET architecture.

The vertical flow of electrical current has a very beneficial impact on both its switching speed and its consumption.

However, the fact that electrical current flows vertically in these new transistors has a very beneficial impact on both their switching speed and their consumption, which, again according to IBM, reduced by up to 85% when compared to the most advanced FinFET devices available today.

Everything seems to be very well tied, and, in addition, this approach avoids the artificiality that emerging technologies often have to put on the table. a clear and reasonably simple idea. Fingers crossed that this technology can be used on a large scale as soon as possible.

More information | IBM Research



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